Designation Staff Physical Design Engineer In Sand Disk In Bangalore :
Job Description :
In this position, the individual will be responsible for providing technical leadership in the Physical Verification, chip finishing and floor-planning aspects of the physical implementation flow. Duties will include complete ownership of full chip floor-planning, Power Planning, Physical verification and Chip finishing. Other activities will include ownership of physical design flow and timing closure for blocks on hierarchical implementation, good knowledge of timing closure, IR/EM Analysis, and Timing/SI Signoff of the block. Ability to work with minimal supervision and at the same time work as part of a larger geographically diverse team is essential. He / She will also drive IP integration strategies that ensure quality and avoid schedule surprises.
Desired Profile :
This position requires a Masters Degree in Electrical Engineering or Computer Science with a minimum of 5 to 7 years of direct experience in Physical design with emphasis on DFM, LVS and DRC.Proficiency in PV flow, tape-out process, working with the foundry on DRC/LVS issues and experience in PERL/TCL/Shell scripting is a must. The individual must have proven hands on experience leading the tape out of multiple large low power hierarchical 65nm/40nm designs. Expertise in Mentor Calibre, Synopsys ICV and Cadence Virtuoso toolset is a must. Good verbal and written communication skills are required.
Experience 7 - 12 Years
Industry Type Semiconductors, Electronics
Role Technical Lead/ Project Lead
Functional Area Engineering Design, R&D
Education UG - B.Tech/B.E. - Any Specialization
PG - M.Tech - Any Specialization
DOCTORATE - Doctorate Not Required
Location : Bengaluru/Bangalore
Keywords Physical design, power planning, physical verification, timing closure
Contact Details:
Contact : Shash
Sandisk : India
Telephone : 9916999907
Email : Shash.dhar@sandisk.com
Website : http://www.sandisk.com/about-sandisk/careers
Job Description :
In this position, the individual will be responsible for providing technical leadership in the Physical Verification, chip finishing and floor-planning aspects of the physical implementation flow. Duties will include complete ownership of full chip floor-planning, Power Planning, Physical verification and Chip finishing. Other activities will include ownership of physical design flow and timing closure for blocks on hierarchical implementation, good knowledge of timing closure, IR/EM Analysis, and Timing/SI Signoff of the block. Ability to work with minimal supervision and at the same time work as part of a larger geographically diverse team is essential. He / She will also drive IP integration strategies that ensure quality and avoid schedule surprises.
Desired Profile :
This position requires a Masters Degree in Electrical Engineering or Computer Science with a minimum of 5 to 7 years of direct experience in Physical design with emphasis on DFM, LVS and DRC.Proficiency in PV flow, tape-out process, working with the foundry on DRC/LVS issues and experience in PERL/TCL/Shell scripting is a must. The individual must have proven hands on experience leading the tape out of multiple large low power hierarchical 65nm/40nm designs. Expertise in Mentor Calibre, Synopsys ICV and Cadence Virtuoso toolset is a must. Good verbal and written communication skills are required.
Experience 7 - 12 Years
Industry Type Semiconductors, Electronics
Role Technical Lead/ Project Lead
Functional Area Engineering Design, R&D
Education UG - B.Tech/B.E. - Any Specialization
PG - M.Tech - Any Specialization
DOCTORATE - Doctorate Not Required
Location : Bengaluru/Bangalore
Keywords Physical design, power planning, physical verification, timing closure
Contact Details:
Contact : Shash
Sandisk : India
Telephone : 9916999907
Email : Shash.dhar@sandisk.com
Website : http://www.sandisk.com/about-sandisk/careers
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